A Chronicle of Silicon

Hardware,
Thinking.

VLSI engineer, 7+ years turning specs into silicon: RTL, verification, timing closure, board bring-up.

Begin Résumé
The Profile
ClassVLSI Engineer
FocusRTL · Validation · Tooling
OriginIndia
Local Time--:--:-- IST

Over 7 years across the full FPGA module lifecycle: requirement gathering, detailed design, RTL/ASIC code porting, testbench coding, prototype testing, pre-silicon validation and SoC integration. I've mentored teams and steered projects end to end, and I'm increasingly convinced the next stretch of that lifecycle gets co-designed with machines.

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The Work
I
SemiCraft
OSS
Deterministic, option-driven RTL generation platform: structured configuration in, lint-checked SystemVerilog/Verilog out, with a live preview and a full explanation of every generated snippet. No prompting, no black box.
II
VLSI-AGKit
OSS
AI agent toolkit for VLSI front-end work: 14 role-based agents and 21 skills covering RTL design, verification, timing closure and CDC, installable into Claude Code, Copilot, Cursor, Gemini CLI and Antigravity.
III
Pre-Silicon Validation: ARM Cortex SoC
FPGA
Timing closure across multiple design revisions, build-time reduction, LINT checks and on-board validation. Memory porting, Python tooling for ILA insertion, and bare-metal/disassembly debug with ARM DStream-ST.
IV
FPGA Regex Pattern-Matching Accelerator
PoC
Proof-of-concept RTL for high-throughput regex matching on network packets: split forward/reverse DFA on an AMD Xilinx Versal device. Architecture, IP-level RTL, UVM simulation in QuestaSim, synthesis/STA/timing closure and board bring-up.
V
RISC-V (Rocket Chip) SoC Design
SoC
IP stitching of UART, SPI, I2C and other serial interfaces onto an AXI4-Lite interconnect. Top-level architecture, block-level UVM simulation, and SoC-level signal tracing for system debug.
The Journey
A Path, Roughly Drawn
2025-
Module Lead, FPGA Design & Validation
Happiest Minds Technologies. Leading FPGA design and validation modules.
2023-25
Senior Engineer, FPGA Design & Validation
Happiest Minds Technologies. FPGA design, verification, and validation flows.
2022
Senior Engineer (VLSI) R&D
Numato Systems, Bengaluru. VLSI R&D, junior to senior in three years.
2021-22
Junior Engineer (VLSI) R&D
Numato Systems. Hands-on RTL design and verification.
2019-21
Associate Engineer (VLSI) R&D
Numato Systems. First industry role, where the VLSI journey began.
2015-19
B.E., Electronics & Communication
BTL Institute of Technology. First Verilog. First testbench. First all-nighter.
Loadout
The Arsenal
Primary
Verilog
VHDL / SystemVerilog
RTL, Testbench · 7Y
Devices
Versal · UltraScale+ · Artix/Kintex/Spartan · Zynq
Xilinx Family
Devices
ECP5 · PolarFire (SoC)
Lattice, Microchip
Design Tools
Vivado · ISE · Libero SoC · Diamond
Implementation
On-Board Debug
Chipscope · DStream-ST
ILA, Baremetal
High-Speed IO
DDR2/3/4 · PCIe · Ethernet · DisplayPort
SPI, I2C · Gigabit
Verification
QuestaSim · ModelSim · UVM
Simulation
Script
Python · Tcl · Batch
Flow Automation
Currently Thinking About
LLMs for RTL · LiteX soft cores · pre-silicon validation tooling
Reading, Tinkering, Writing
Lore
Scrolls
AI-Powered VIP Development: Building a UART VIP with VLSI-AGKit & Antigravity
Feb 2026
→
Bridging Logic & AI: The Birth of VLSI-AGKit
Jan 2026
→
Building Neural Silicon Part 1: Forging the Silicon Cortex
Jan 2026
→
Final Stretch

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